The present invention relates to a bus system employed in information processing apparatuses such as a workstation, a personal computer, and a word processor.
The bus system disposed in the information processing apparatus is configured; like a bus system described in a report xe2x80x9cEISAxe2x80x9d written by L. Brett Glass in pages 417 to 424 of xe2x80x9cBYTExe2x80x9d, Volume 14, Number 12 (1989); such that memory and system buses are respectively connected to a processor bus or processor and memory buses are respectively linked to the system bus.
In the former constitution, during a cooperative action of the system and memory buses, namely, during the so-called direct memory access (DMA), the processor bus cannot operate in an independent fashion, which consequently leads to a deterioration of the utilization efficiency of the processor bus. In the latter case, on the other hand, during a cooperative operation of the processor and memory buses i.e. during the so-called main memory access, the system bus cannot operate in an independent manner, thereby leading to a problem of a deterioration of the utilization efficiency of the system bus.
In this regard, the configuration and the problems of the conventional bus system will be described in detail later by referring to drawings.
It is therefore an object of the present invention to provide a bus system for use with an information processing apparatus capable of maximizing the utilization efficiency of each bus.
Another object of the present invention is to provide a bus system in which a cooperative action of a processor bus and a memory bus and an independent operation of a system bus can be accomplished at the same time.
Still another object of the present invention is to provide a bus system in which a cooperative action of a system bus and a memory bus and an independent operation of a processor bus can be accomplished at the same time.
Still another object of the present intention is to provide a bus system for use with an information processing apparatus in which when there is established an interconnection between at least three buses including three kinds of buses i.e. system, memory, and processor buses, the utilization efficiency of each bus can be maximized.
In order to achieve the objects above, according to the present invention, there is established a configuration in which an interconnection is constituted in the form of a three-way connection with three types of buses including the processor, memory, and system buses such that while two arbitrary types of buses are achieving a cooperative operation, the bus of the other type can operate in an independent manner.
That is, according to the present invention, there is disposed control means forming a three-way connection of three kinds of buses including a processor bus linked to at least one processor, a memory bus connected to a main memory, and a system bus linked to at least one connected device such as an input/output (I/O) device, thereby establishing interconnections between various buses.
In other words, according to the present invention, a bus system for use with an information processing apparatus includes three kinds of buses including a processor bus linked to at least one processor, a memory bus connected to a main memory, and a system but linked to at least one connected device and connection control means for interconnecting these buses to each other.
In accordance with the present invention, the connection control means includes data path switch means for transferring data through the data buses respectively of the three kinds of buses thus interconnected to each other and a bus/memory connection controller for transferring control signals and addresses through the control and address buses respectively of the three kinds of buses and for generating a data path control signal to be supplied to the data switch means.
Preferably, the data switching means and the bus/memory connection controller are configured respectively as integrated circuits or are combined with each other in an integrated circuit.
Furthermore, according to the present invention, the number of the buses of each kind need not be limited to one, namely, even when there are disposed a plurality of buses of either one of the three kinds, the connection control means may be similarly constructed to establish an interconnection between these buses.
In the configuration of the present invention described above, with an interconnection of the three kinds of buses including the processor, memory, and system buses, for example, when a processor on the processor bus conducts a processor/main memory access to access the main memory on the memory bus, data is transferred only via the processor and memory buses i.e. the system bus is not used for the data transfer. Consequently, the system bus can operate in an independent fashion. On the other hand, when a connected device on the system bus achieves a DMA to access the main memory on the memory bus, data is transferred only through the system and memory buses. That is, the processor bus is not employed for the transfer and hence can achieve an independent operation.
As a result, it is possible to develop the maximum utilization efficiency for each of the three kinds of buses.